MN-ADC based on high-reliable 2T2R synapse structure

With the ever-growing demands for sampling rate, conversion resolution, as well lower energy consumption, memristor-based neuromorphic analog-to-digital converters (MN-ADC) becomes one of most potential approaches to break bottleneck traditional ADCs. However, online trainable MN-ADCs are not designed be easily integrated into 1T1R crossbar array, meanwhile suffering from device non-idealities, which makes it difficult realize high-speed and accurate conversion. To overcome these issues, this paper proposes a high-reliable 2T2R synaptic structure. And through dedicated structure, we construct 4-bit MN-ADC that allows alternate conversions adjustments in single clock period, can significantly mitigate effects non-idealities on dynamic performance. More importantly, structure perfectly compatible with arrays. Simulation results demonstrate validity proposed MN-ADC, achieves ENOB 3.77 bits, INL 0.16 LSB, DNL 0.07 LSB.